1. Field of the Invention
The present invention relates to a liquid crystal display LCD device, and more particularly, to an LCD device and a method for fabricating the same to improve a yield with a decreased process time.
2. Discussion of the Related Art
Recent efforts have been made to research and develop various types of flat display devices, such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some types of flat display devices have already been used as displays in various applications.
Among the types of flat display devices, liquid crystal display (LCD) devices have been most widely used due to its advantageous characteristics of thin profile, lightness in weight, and low power consumption, whereby the LCD devices provides a substitute for a Cathode Ray Tube (CRT). In addition to mobile type LCD devices such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
Despite various technical developments in the LCD technology having applications in different fields, research in enhancing the picture quality of the LCD device has been, in some respects, lacking as compared to other features and advantages of the LCD device. In order to use LCD devices in various fields as a general display, the key to developing LCD devices depends on whether LCD devices can realize a high quality picture, such as high resolution and high luminance with a large-sized screen, while still maintaining lightness in weight, thin profile, and low power consumption.
Generally, the LCD device includes an LCD panel for displaying a picture image, and a driving part for applying a driving signal to the LCD panel. The LCD panel includes first and second glass substrates being bonded to each other at a predetermined interval therebetween, and a liquid crystal layer formed between the first and second glass substrates by injection of liquid crystal.
The first glass substrate (TFT array substrate) includes a plurality of gate and data lines, a plurality of pixel electrodes, and a plurality of thin film transistors. The plurality of gate lines are formed at fixed intervals in a first direction on the first glass substrate, and the plurality of data lines are formed at fixed intervals in a second direction perpendicular to the first direction. Then, the plurality of pixel electrodes, which are arranged in a matrix-type configuration, are respectively formed in pixel regions defined by the plurality of gate and data lines crossing each other. The plurality of thin film transistors are switched according to signals of the gate lines for transmitting signals of the data lines to the respective pixel electrodes.
The second glass substrate (color filter substrate) includes a black matrix layer that excludes light from regions except the pixel regions of the first substrate, R(red)/G(green)/B(blue) color filter layer displaying various colors, and a common electrode to obtain the picture image. In a case of an In-Plane Switching (IPS) mode LCD device, the common electrode is formed on the first glass substrate.
Next, a predetermined space is maintained between the first and second glass substrates by spacers, and the first and second substrates are bonded to each other by a seal pattern having a liquid crystal injection inlet. At this time, the liquid crystal layer is formed according to a liquid crystal injection method, in which the liquid crystal injection inlet is dipped into a vessel having liquid crystal while maintaining a vacuum state in the predetermined space between the first and second glass substrates. That is, the liquid crystal is injected between the first and second substrates by an osmotic action. Then, the liquid crystal injection inlet is sealed with a sealant.
Meanwhile, the LCD device is driven according to the optical anisotropy and polarizability of liquid crystal material. Liquid crystal molecules are aligned using directional characteristics because the liquid crystal molecules each has long and thin shapes. In this respect, an induced electric field is applied to the liquid crystal for controlling the alignment direction of the liquid crystal molecules. That is, if the alignment direction of the liquid crystal molecules is controlled by the induced electric field, the light is polarized and changed by the optical anisotropy of the liquid crystal, thereby displaying the picture image. In this state, the liquid crystal is classified into positive (+) type liquid crystal having positive dielectric anisotropy and negative (−) type liquid crystal having negative dielectric anisotropy according to electrical characteristics of the liquid crystal. In the positive (+) type liquid crystal, a longitudinal (major) axis of a positive (+) liquid crystal molecule is arranged in parallel to the electric field applied to the liquid crystal. Meanwhile, in the negative (−) type liquid crystal, a longitudinal (major) axis of a negative (−) liquid crystal molecule is arranged in perpendicular to the electric field applied to the liquid crystal.
Hereinafter, a related art LCD device will be described with reference to the accompanying drawings.
FIG. 1 illustrates an expanded plan view of a unit pixel of an LCD device according to the related art. FIG. 2 illustrates a cross sectional view along 1-1′ of FIG. 1. FIGS. 3A to 3E illustrate cross sectional views of a process for fabricating an LCD device according to the related art.
As shown in FIGS. 1 and 2, the LCD device according to the related art includes a lower substrate 20 and an upper substrate. The lower substrate 20 includes a gate line 21, a data line 24, a pixel electrode 27, and a thin film transistor TFT. The gate line 21 is formed perpendicular to the data line 24, to define a unit pixel region P. Also, the pixel electrode 27 is formed in the unit pixel region P, and the thin film transistor TFT is formed at a crossing of the gate and data lines 21 and 24.
The thin film transistor TFT is comprised of a gate electrode 21a, a gate insulating layer 22, an active layer 23, a source electrode 24a, and a drain electrode 24b. The gate electrode 21a protrudes from the gate line 21, and the gate insulating layer 22 is formed on an entire surface of the lower substrate 20. Then, the active layer 23 is formed on the gate insulating layer 22 over the gate electrode 21a. The source electrode 24a, which protrudes from the data line 24, overlaps one side of the active layer 23. The drain electrode 24b, which is formed at a predetermined interval from the source electrode 24a, overlaps the other side of the active layer 23. In addition, an ohmic contact layer 23a is formed between the active layer 23 and the source electrode 24a, and between the active layer 23 and the drain electrode 24b. 
Furthermore, a first storage electrode 24c is formed on the gate insulating layer 22 above a preceding gate line.
A passivation layer 25 is formed on the entire surface of the lower substrate 20 including the thin film transistor TFT. Also, a first contact hole 26a is formed in a predetermined portion of the drain electrode 24b, and a second contact hole 26b is formed in a predetermined portion of the first storage electrode 24c. 
A pixel electrode 27 is formed in the pixel region on the passivation layer 25 such that the pixel electrode 27 is connected with the drain electrode 24b through the first contact hole 26a. Also, a second storage electrode 28 is formed by extending the pixel electrode to the preceding gate line including the second contact hole 26b. 
The pixel electrode 27 and the second storage electrode 28 are formed of a transparent conductive metal having a great transmittance of light, for example, indium-tin-oxide ITO.
Although not shown, the upper substrate is formed opposite to the lower substrate 20. The upper substrate includes a black matrix layer, an RGB color filter layer, and a common electrode. The black matrix layer is provided to prevent light from leaking in other portions except the pixel region P. The RGB color filter layer is formed to represent colors, and the common electrode is formed to realize images.
A method for fabricating the LCD device according to the related art will be described as follows.
First, as shown in FIG. 3A, a conductive metal is coated on the transparent lower substrate 20, and is then patterned by photolithography using a first mask. As a result, the gate line 21 is formed in one direction on the lower substrate 20. In this state, the gate electrode 21a is formed at one side of the gate line 21.
After that, as shown in FIG. 3B, the gate insulating layer 22 is formed on the entire surface of the lower substrate 20 including the gate line 21. At this time, the gate insulating layer 22 may be formed of silicon nitride SiNx or silicon oxide SiO2.
After that, a semiconductor layer (mixture of amorphous silicon and impurity amorphous silicon) is formed on the gate insulating layer 22.
Subsequently, the semiconductor layer is patterned by photolithography using a second mask. Thus, the active layer 23 of an island shape is formed above the gate electrode 21a. 
After that, as shown in FIG. 3C, a conductive metal is deposited on the entire surface of the lower substrate 20 including the active layer 23, and is then patterned by photolithography using a third mask. As a result, the data line 24 is formed perpendicular to the gate line 21, the source electrode 24a which protrudes from one side of the data line 24 overlaps one side of the active layer 23, and the drain electrode 24b overlaps the other side of the active layer 23. At this time, the drain electrode 24b is formed at a predetermined interval from the source electrode 24a. Also, the first storage electrode 24c is formed above a predetermined portion of the preceding gate line 21.
When etching the data line 24, the source electrode 24a, and the drain electrode 24b, the impurity amorphous silicon is over-etched. Thus, the ohmic contact layer 23a is formed between the source electrode 24a and the active layer 23, and between the drain electrode 24b and the active layer 23.
In the above process, the gate line 21 is formed perpendicular to the data line 24, thereby defining the pixel region P.
As shown in FIG. 3D, the passivation layer 25 is deposited on the entire surface of the lower substrate 20 including the data line 24. Subsequently, the first and second contact holes 26a and 26b are formed to expose the drain electrode 24b and the first storage electrode 24c, respectively.
Referring to FIG. 3E, a transparent conductive layer is deposited on the passivation layer 25, and is selectively removed by photolithography using a fifth mask, thereby forming the pixel electrode 27 in the pixel region. The pixel electrode 27 of the transparent conductive layer extends to the preceding gate line including the second contact hole 26b, thereby forming the second storage electrode 28.
Through the above-mentioned process according to the related art, the five masks are totally required so that it has a limitation in improvement of yield.